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d a t a sh eet preliminary speci?cation 2002 may 06 integrated circuits tza1032 laser driver and controller circuit
2002 may 06 2 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 contents 1 features 2 general description 3 ordering information 4 quick reference data 5 block diagram 6 pinning 7 functional description 7.1 the i 2 c-bus interface 7.2 interrupt request 7.3 soft reset and power-down 7.4 the phase locked loop 7.5 the differential receiver 7.6 the rlc decoder 7.7 write strategy generator 7.8 laser power control 8 functional diagram 9 characteristics 10 application information 11 bonding pad locations 12 data sheet status 13 definitions 14 disclaimers 15 purchase of philips i 2 c components
2002 may 06 3 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 1 features separate 3.3 v digital, analog and output driver power supplies selective power-down of internal functions via i 2 c-bus for power saving low voltage-swing of the differential run length limited code (rlc) inputs for high speed transmission and good electromagnetic compatibility high-impedance input switching to control two or more tza1032 ics in parallel for double writer applications supports i 2 c-bus interface up to 400 kbits/s with block transfer feature in slave mode only 3.3 and 5 v tolerant input logic supports any rlc code with run lengths from 1 to 15 automatic write-read switching for run lengths 3 16 channel decoding rate up to 105 mbits/s, according to dvd 4 look back function to enable write pre-compensation by data dependent write strategy with a land-pit compensation up to five supports forced erase (fe) mode for quick initialisation of disc fixed propagation delay within rlc clock periods to allow accurate data linking on disc supports cd-r, cd-rw, dvd+rw, dvd-r, dvd-rw and dvr formats or any comparable existing or future format programmable write strategy via i 2 c-bus; completely flexible up to a maximum of two output level transitions per rlc clock period pulse timing resolution of 2 ns at 500 mhz internal clock minimum pulse width of 4 ns at 500 mhz internal clock four programmable threshold current levels with an 8-bit resolution, and eight programmable delta levels with an 8-bit resolution independent laser threshold and laser delta current control programmable modulation unit pointer memory mapping to allow compact write strategy coding pll oscillator features a self-learning oscillator mode for non-locked operation during read wide frequency range: pll locking factor 3 2.5 two output channels, delta and threshold current levels, each capable of delivering 240 ma delta and 200 ma threshold peak current to the output rise and fall times of 1 to 2 ns, depending on package and laser typical output resistance of 120 w programmable current step size for a threshold level of 0 to 1 ma at a 16-bit resolution, and a delta level of 0 to 1.2 ma at an 8-bit resolution internal modulator up to 565 mhz forward sense (fs) laser power control (lpc) loop to compensate laser drift due to temperature and aging internal set point generation to allow read-write switching without any transient effects digital lpc algorithm based on fs feedback single forward sense diode connection programmable fs input current gain to allow for spread in fs efficiency supports running optimum power control (opc) loop, so called alpha loop, to monitor and control the quality of writing programmable loop bandwidths: up to 1 khz for the lpc, and up to 50 khz for the alpha loop programmable minimum and maximum limiting of laser currents and running opc range programmable opc stepper. 2 general description the tza1032 is a laser driver circuit which is intended for a wide range of recordable and re-writable optical drives. figure 3 shows a function diagram of tza1032 in relation to a disc recording system. the tza1032 is intended to be located close to the laser diode on the optical pick-up unit (opu). it can be used in cd-r/rw systems with 1 ,2 ,4 ,8 ,12 ,16 and 24 (24 is not guaranteed yet: evaluation pending) speed and in dvd-r/rw systems with 1 ,2 and 4 speed (4 is not guaranteed yet). furthermore, it is suitable for future standards like dvr.
2002 may 06 4 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 the tza1032 fulfils three main functions: drives the laser with a sequence of programmable write strategy pulses with high timing accuracy and high peak current levels encodes the input modulated data to a sequence of write strategy pulses. this encoding is flexible with respect to input modulation code (efm, efmplus, 17 pp, etc.). any rlc with run lengths in the range from 1 to 15 is possible. the write strategy is programmable with high flexibility for cd-r/rw, dvd-r/rw, dvr or other optical recording systems using comparable write strategies. for this purpose the tza1032 includes two random access memories (rams) which can be loaded (non real-time) via an i 2 c-bus from a pc or microcontroller controls the exact light power levels coming from the laser and controls the exact power absorbed by the disc during recording. this is not trivial since the laser characteristics (both threshold and gain) are strongly temperature dependent. a first control loop controls the laser power levels based on the signal from a forward sense diode (fs control). this will make the laser virtually temperature and aging independent. the loop is fully self-contained, only an external forward sense diode must be connected. a second control loop controls the laser power based on an alpha signal, generated by additional electronics based on signals from the diode during writing. it is primarily intended to compensate for writing performance variations due to imperfections in the optical path and/or disc (e.g. finger prints). the alpha signal is a measure of the power absorption of the disc material during the writing process or in general of the writing quality on the disc. for this second loop, a method of stepping the set point under external control is provided. the tza1032 contains a programmable counter that can be clocked via the external opc-strobe (pin opc). this function is typically used during opc in order to calibrate the optimum laser writing power. when required, non-real time control is possible via an interrupt feedback signal at pin irq. the tza1032 can supply the analog, digital and driver part separately to obtain maximum performance. the tza1032 features three independent power supplies. these are the analog and digital power supplies and a local power supply for the laser driver function. the supplies can be delivered separately to obtain maximum output performance of the tza1032 in environments with large and highly dynamic current flows. the driver supply has no accompanying ground because the laser driver block only sources current to the laser. ensure that all power supply pins are connected to the appropriate voltage rails. for evaluation purposes only (by special request) the tza1032 can be delivered in a lqfp64 package. 3 ordering information type number package name description version TZA1032UK - bare die with solder bumps -
2002 may 06 5 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 4 quick reference data symbol parameter condition min. typ. max. unit v dd[1 to 3] output supply voltage 3.0 3.3 3.6 v i out[1 to 3] output current (threshold) 1 - 200 ma output current (delta) 0 - 240 ma r out[1 to 3] output resistance - 120 -w t r ,t f rise and fall time depends on package and load -- 1to2 ns rl min decodable run length 1 - 15 b lpc( - 3db) - 3db lpc bandwidth - 1 - khz b alpha( - 3db) - 3db alpha bandwidth - 50 - khz f mod modulator frequency pll locked to external clock 250 - 565 mhz pll in current controlled oscillator (cco) mode 240 - 440 mhz t w(min) minimum pulse width 4 -- ns t res timing resolution 2 -- ns
2002 may 06 6 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 5 block diagram mgw501 handbook, full pagewidth ameas rlc decoder i 2 c-bus interface aez sample timing generator scl lpc loop; alpha loop and opc fs_adc alpha_adc lasp_dac i_delta_dac_ref i_threshold_dac_ref p_writeset rdwr p_readset lcd clock laser control analog fs lasp opc sda i2c_a0 irq rlc differential receiver datap datan clkp clkn data delta (8 bits) threshold clk rlc to ws & setpoint power converter reference dacs threshold (16 bits) delta (8 bits) multiplying current dacs out[1 to 3] rdwr es to all blocks supply test interface refh v dd digital power v dda v ssa v ddd v ssd lca clock analog ref analog ref reference_clock feedback_clock lock_clock strategy_clock output_clock lcd clock refl es test_in [ 1 to 0 ] test [ 2 to 0 ] test_clk test_out [ 1 to 0 ] fsplus fsmin ivrefcon ivcon power-on reset v ss cfs TZA1032UK n.c. 43 analog power 33 2 2 3 3 3 8, 17, 21, 38 3, 18, 47 22, 27, 46 19, 30, 48 16 41 14 15 40 37 35 34 33 45 32 31 23 24 26 25 43 44 42 1, 2, 49 50, 51, 52 5, 6, 7 9, 10 13 11, 12 36 39 29 28 20 4 analog reference laser control digital pll fig.1 block diagram.
2002 may 06 7 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 6 pinning symbol pad type description v dd2 1 p laser driver power supply v dd3 2 p laser driver power supply v ssd3 3 p ic digital ground v ss 4 p laser driver ground v ddd3 8 p ic digital power supply irq 14 o interrupt request; digital output (open drain sink). irq is an active low interrupt service request output line to the microprocessor. this line is set (made low) by internal laser driver events and is cleared (made high) when a register in the laser driver is read via i 2 c-bus. opc 15 i opc strobe; digital input with pull-down resistor. the system controller during opc issues the opc (strobe) signal. this signal tells the laser driver that a step in a set point value should be made during opc mode. i2c_a0 16 i digital input pin with pull-down resistor whose function is to select which i 2 c-bus address range applies to the ic. this allows two laser drivers to be used in parallel on one i 2 c-bus. this pin is also used as test mode selection pin for test mode. v ddd1 17 p ic digital power supply v ssd1 18 p ic digital ground v ssa1 19 p ic analog ground v ssd4 20 p not connected v ddd4 21 p ic digital power supply v dda1 22 p ic analog power supply clkn 23 i clock pulse; analog current input. the anti-phase clock signal is used together with clkp to allow balanced transmission. clkp 24 i clock pulse; analog current input. provides clock reference for efmplus data plus the clock reference for the internal pll. datap 25 i data input; analog current input. this is the input for the run length variable code (in non-return to zero form) from which the laser driver knows which laser pulses to generate. datan 26 i data input; analog current input. the anti-phase data signal (clkn) used together with datan to allow balanced transmission. v dda2 27 p ic analog power supply v ssa2 30 p ic analog ground refh 31 o band-gap reference output (for external smoothing capacitor) refl 32 o band-gap ground connection (for external smoothing capacitor) cfs 33 o capacitor forward sense; analog connection for external smoothing capacitor. an external capacitor of 560 pf combined with an internal resistor of 70 k w can be used to create a rc ?lter for the fs input before the adc unit in order to prevent slew-rate effects. this capacitor is placed between this pin and refl.
2002 may 06 8 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 ameas 34 i alpha measure; analog current sink input. ameas (alpha measure) is the value of the measured disk writing quality. this is used in the alpha control loop in order to regulate the actual laser power as a function of non-laser system and medium drift. lasp 35 o laser power; analog current source output. pin lasp indicates the laser power level. the read power is constant and the write power level (which is added during laser driver write mode) is alpha corrected. this signal is used in order to normalise signals with respect to laser power. aez 37 i alpha error zero; digital input with pull-down resistor. depending on the programming of an internal mode bit one of two effects occurs when this input is asserted. alpha error zero (aez): the output of the alpha error adder is forced to zero. alpha set zero (asz): the alpha error adder positive input (i.e. the alpha set point) is forced to zero. v ddd2 38 p ic digital power supply scl 40 i digital input for i 2 c-clock (the laser driver is a slave device) sda 41 i/o digital bi-directional port with open-drain sink output for i 2 c-bus data rdwr 42 o read-write; digital output line. this signal indicates whether the laser driver is in read mode (high) or write mode (low). es 43 o analog output line. this signal indicates when valid signals from the photo-detector can be expected for sampling purposes (used in cd-r applications). es 44 o analog output line. the es anti-phase signal used together with es to allow balanced transmission. fs 45 i forward sense; analog current sink input. this is the value of the measured laser power (e.g. measured by a photodiode which receives a set fraction of laser output directly). this is used in the laser power control loop in order to regulate the actual laser power to a given set of values as a function of laser temperature drift. v dda3 46 p ic analog power supply v ssd2 47 p ic digital ground v ssa3 48 p ic analog ground v dd1 49 p laser driver power supply out1 50 o analog current output to the laser out2 51 o analog current output to the laser out3 52 o analog current output to the laser laser driver ic test pads test2 5 i digital input bus for test mode control. normal functional mode (normal application use) is: all pins with an internal pull-down resistor and code = 0. test1 6 i digital input bus for test mode control. normal functional mode (normal application use) is: all pins with an internal pull-down resistor and code = 0. test0 7 i digital input bus for test mode control. normal functional mode (normal application use) is: all pins with an internal pull-down resistor and code = 0. symbol pad type description
2002 may 06 9 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 test_in1 9 i digital input bus with internal pull-down resistors for test data input. high-impedance state in functional mode. test_in0 10 i digital input bus with internal pull-down resistors for test data input. high-impedance state in functional mode. test_out1 11 o digital output bus for test data output. high-impedance state in functional mode. test_out0 12 o digital output bus for test data output. high-impedance state in functional mode. test_clk 13 i digital input pin with internal pull-down resistor for test data clock. high-impedance state in functional mode. ivcon 28 o analog current output related to the pll loop-?lter. high-impedance state in functional mode. ivrefcon 29 o analog current output related to the pll loop-?lter. high-impedance state in functional mode. fsplus 36 o analog voltage output from lca fs/alpha pre-amp circuit. high-impedance state in functional mode. fsmin 39 o analog voltage output from lca fs/alpha pre-amp circuit. high-impedance state in functional mode. symbol pad type description
2002 may 06 10 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 handbook, full pagewidth TZA1032UK mgw503 43 44 45 46 40 41 42 47 48 49 50 51 52 23 22 21 20 26 25 24 19 18 17 16 15 14 12345678910 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 scl sda rdwr es datap datan es fs clkp clkn i2c_a0 aez v dda1 v dda2 v dda3 v ddd4 v ddd3 test2 test0 test_in1 test_in0 test_out0 test_out1 test1 test_clk v ddd2 v ddd1 opc refl ivrefcon ivcon refh lasp v ss v ssa3 v ssd2 v ssa2 v ssa1 irq v ssd3 v ssd1 out1 out2 out3 v dd3 v dd2 v dd1 ameas fsmin fsplus cfs fig.2 bare die with solder bumps (flip-chip). pad number 20 is not connected.
2002 may 06 11 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 7 functional description 7.1 the i 2 c-bus interface the tza1032 has two possible i 2 c-bus addresses that can be selected via pin i2c_a0, an active high digital cmos input. this allows two tza1032 ics to be independently applied using the same i 2 c-bus (e.g. for double write applications), one with pin i2c_a0 high and the other with pin i2c_a0 low. the tza1032 operates as a slave only i 2 c-bus device. table 1 tza1032 i 2 c-bus addresses each i 2 c-bus register has an 8-bit register address bus. the various modes in which an external controller can use the i 2 c-bus interface are shown in table 2. the special ram write mode allows fast block transfer of data via one single i 2 c-bus register address. table 2 i 2 c-bus communication modes supported by tza1032 7.2 interrupt request the irq is built as an active low open-drain output pin so it can be linked to the system controller together with similar signals in a wired-or approach. an irq register is present to select the conditions which can cause the irq line to be active. possible conditions for an interrupt can be overrun or under-run of threshold or delta laser current or several other selectable conditions. the status register allows extra signals to be monitored in non-interrupt mode (e.g. by polling). the irq and status registers in combination with the irq line allow a very efficient way of controlling tza1032. in addition, the irq_enable register allows selectable masking of most of the irq conditions to the irq line. i2c_a0 i 2 c-bus write address i 2 c-bus read address 0 = low 1101 1100 (dch) 1101 1101 (ddh) 1 = high 1101 1110 (deh) 1101 1111 (dfh) i 2 c-bus mode i 2 c-bus information write start; tza1032_write_address; acknowledge; register_address (n); acknowledge; data_to_register_address (n); acknowledge; stop incremental write start; tza1032_write_address; acknowledge; register_address (n); acknowledge; data_to_register_address (n); acknowledge; data_to_register_address (n + 1); acknowledge; .... ; data_to_register_address (n + r); acknowledge; stop ram write start; tza1032_write_address; acknowledge; register_address (= ram x), acknowledge; data_to_ram x (0), acknowledge; data_to_ram x (1), acknowledge; .... ; data_to_ram x (m); acknowledge; stop read start; tza1032_write_address; acknowledge; register_address (n); acknowledge; stop start; tza1032_read_address; acknowledge; data_from_register_address (n); ac kno wledge; stop successive read start; tza1032_write_address; acknowledge; register_address (n); acknowledge; start; tza1032_read_address; acknowledge; data_from_register_address (n), acknowledge; data_from_register_address (n); acknowledge; .... ; data_from_register_address (n); ac kno wledge; stop
2002 may 06 12 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 7.3 soft reset and power-down tza1032 has a soft reset register that can reset most of the internal blocks, and is automatically synchronized with the i 2 c-bus scl input. most of the blocks in the tza1032 are provided with a power-down input. the ic features a special power-down register which can be programmed via i 2 c-bus. an active bit in the register causes a block to go into a low dissipation standby mode. this offers the user the possibility to save power when tza1032 operates in a register mode (e.g. during read). 7.4 the phase locked loop the pll is phase locked to the incoming rlc clock signal. a single external clock signal is sufficient for a complete task of tza1032. the pll unit provides all internal clocking with the exception of the i 2 c-bus interface that can run on its own scl clock. the pll can be used in closed loop or as a stable open-loop oscillator (in read mode for example) when no input clock is present. for this purpose the pll features a self-learning oscillator mode for non-locked operation. furthermore, the pll is designed for wide range frequency locking (factor 3 2.5). the frequency multiplication factor is programmable for flexible selection of write strategy timing resolution for different standards (cd 1 to 24 , dvd 1 , 2 , 4 and dvr). for pll characteristics see table 3 for the possible pll frequencies and write strategy resolutions with respect to the incoming rlc clock. the tza1032 features are much more flexible than shown in table 3. the pll frequency and write strategy resolution can be programmed according to the specific requirements of the user. table 3 examples of pll clock ratio programming note 1. the write strategy resolution is defined as the number of bits per rlc clock period. 7.5 the differential receiver a differential rlc receiver (drx) with low voltage-swing is present to allow high data rates in combination with low electromagnetic interference. the receiver features impedance matching with typical flex foils. furthermore, single side operation is optionally possible by connecting additional external resistors. high-impedance input switching allows two or more tza1032 ics to operate in parallel. the high-impedance input switch is controlled by a single i 2 c-bus control register that can individually select drx clock and/or data lines for high-impedance mode. a high-impedance input mode is also entered during reset or power-down. standard rlc frequency f rlc (mhz) pll frequency f o (mhz) write strategy resolution (1) cd 1 4.3218 518.616 8 cd 2 8.6436 518.616 8 cd 4 17.2872 553.1904 8 cd 8 34.5744 553.1904 8 cd 12 51.8616 414.8928 8 cd 16 69.1488 553.1904 8 cd 24 103.7232 414.8928 4 dvd 1 26.16 523.2 20 dvd 2 52.32 523.2 10 dvd 2.5 65.4 392.4 6 dvd 4 104.64 418.56 4 dvr-1 65.625 525 8 dvr-2 93.75 562.5 6
2002 may 06 13 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 table 4 truth table for rlc differential receiver; note 1 note 1. x = dont care; l = low; h = high. 7.6 the rlc decoder the rlc decoder and write strategy generator feature a look back function to enable write pre-compensation by data dependent write strategies. the write strategy for the current received run length (rlc n ) depends on the previous received run length (rlc n - 1 ). table 5 shows that tza1032 is capable of decoding 64 possible combinations of rlc n and rlc n - 1 including a read state. the read state is entered after detecting run lengths 3 16. the decoder automatically toggles between the status write and erase in normal writing mode, and the rlc data inputs can be made edge sensitive only, or edge and level sensitive. it should be noticed that erase strategies are possible. a forced erase mode can be entered via i 2 c-bus for quick disc initialisation. the rlc decoder (and the complete tza1032) have a fixed propagation delay of 28 rlc clock periods to allow accurate data linking on disc. table 5 list of possible rlc decoder combinations; note 1 note 1. x = dont care; e = erase; w = write. clock input power-down high_z high_z_clk r eset out bias input switch clkp l l l h h on closed clkn l l l h l on closed x h x x x h off open (high impedance) x l h x x h on open (high impedance) x l x h x h on open (high impedance) x l x x h h on open (high impedance) rlc n rlc n - 1 effect rlc n rlc n - 1 effect rlc n rlc n - 1 effect rlc n rlc n - 1 effect read x 0 e8 x 16 w2 e3 32 w5 e1 48 e1 x 1 e9 x 17 w2 e4 33 w5 e2 49 e2 x 2 e10 x 18 w2 e5 34 w5 e3 50 e3 w3 3 e11 x 19 w2 x 35 w5 e4 51 e3 w4 4 e12 x 20 w3 e1 36 w5 e5 52 e3 w5 5 e13 x 21 w3 e2 37 w5 x 53 e3 x 6 e14 x 22 w3 e3 38 w6 x 54 e4 w3 7 e15 x 23 w3 e4 39 w7 x 55 e4 w4 8 w1 e1 24 w3 e5 40 w8 x 56 e4 w5 9 w1 e2 25 w3 x 41 w9 x 57 e4 x 10 w1 e3 26 w4 e1 42 w10 x 58 e5 w3 11 w1 e4 27 w4 e2 43 w11 x 59 e5 w4 12 w1 e5 28 w4 e3 44 w12 x 60 e5 x 13 w1 x 29 w4 e4 45 w13 x 61 e6 x 14 w2 e1 30 w4 e5 46 w14 x 62 e7 x 15 w2 e2 31 w4 x 47 w15 x 63
2002 may 06 14 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 7.7 write strategy generator the write strategy generator makes use of pointer memory mapping to allow compact write strategy coding. only 1600 bytes have to be transferred to tza1032 to load the most complex write strategy including write pre-compensation. due to the pointer memory structure common strategies can be loaded in an even more compact manner (e.g. cd strategies). loading can be done efficiently via i 2 c-bus block transfer mode. the write strategy code includes: data for selection of output power levels from 4 threshold and 8 delta values (these 8-bit values can be programmed asynchronously via i 2 c-bus) pulse timing information modulation information. the modulation information enables the user to switch on modulation in pre-selected parts of the write strategy on a real time basis. the modulation amplitude can be programmed asynchronously via i 2 c-bus. 7.8 laser power control the forward sense diode (fsd) is a reversed biased diode that receives a small percentage of the laser output light and converts it into a current. the fsd can be connected directly to the tza1032 without additional components. the tza1032 features a current input with programmable gain (6-bit resolution). furthermore a 12-bit adc is used. internal set point generation is present to allow read-write switching without any transient effects. a digital loop filter with programmable loop gain is used. this allows tailoring of loop bandwidth according to the requirements of the application. a unique laser power control algorithm is used. this algorithm ensures not only average power control but it really makes the laser virtual temperature and aging independent for any possible write strategy. this loop operates with or without the alpha (running opc) loop. the tza1032 supports a full running optimum power control loop when required by the user. the loop is also referred to as the alpha loop. the input signal is based on disc absorption measurements (ameas). this signal is processed in a similar way as the fs input current. a current input is provided with programmable gain (4-bit) and an 8-bit adc is used. again a digital loop filter with programmable loop gain is used. this allows tailoring of loop bandwidth according to the requirements of the application. the alpha loop does not interfere with the fs laser power control loop. therefore, both control loops can be used simultaneously. the set point is programmable via i 2 c-bus or is under control of a programmable opc stepper.
2002 may 06 15 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 8 functional diagram mgw500 u ll pagewidth i 2 c-bus interface pll por alpha loop timing & control laser power setpoint generator digital loop filtering lpc digital loop filtering alpha photo detector & preamps disk efm(p) data source (encoder) opc, aez scl, sda, irq, i2c_a0 alpha measure (ameas) rlc to ws converter threshold current reference multiplying current dacs threshold delta delta_ref rlc decoder alpha setpoint & opc stepper delta current reference alpha measure processing + + + + + + + - - + tza1032 fs es, es, rdwr, lasp clock and data (clkp, clkn, datap, datan) out laser forward sense laser light laser light v fs fig.3 functional diagram of tza1032 in relation to a disc recording system.
2002 may 06 16 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 9 characteristics note 1. use low range cco mode only. symbol parameter conditions min. typ. max. unit current driver v dd[1 to 3] output supply voltage 3.0 3.3 3.6 v i out[1 to 3] output current (threshold) 1 - 200 ma output current (delta) 0 - 240 ma r out[1 to 3] output resistance - 120 -w t r ,t f rise and fall times depends on package and load -- 1to2 ns pll f o(r) pll output frequency (1) read mode 240 375 440 mhz f o(w) pll output frequency write mode 320 523.2 565 mhz f i(rlc) pll input frequency 0 26.16 105 mhz fs buffer and adc combination v fs voltage at pin fs virtual ground 1.220 1.225 1.230 v i fs current at pin fs 0 1000 4000 m a dc input current code - 2048 - 0 -m a code 2047; nominal gain - 1000 -m a n resolution signed - 12 - bit b - 3db analog bandwidth 3.08 4.06 5.64 khz reg_fs programmable gain register 6 bits 0 - 63 alpha buffer and adc i alpha input current into pin ameas 0 100 400 m a v alpha input voltage virtual ground 1.3 1.4 1.5 v n resolution signed - 8 - bit i_alpha dc input current code - 128 - 0 -m a code 127; nominal gain - 100 -m a b - 3db analog bandwidth 520 650 850 khz alpha_reg programmable gain register 4 bits 0 - 15 drx input i drxd(hiz) drx data input current high-impedance mode 0 0 100 m a i drxc(hiz) drx clock input current high-impedance mode 0 0 100 m a v data drx data input voltage low-impedance mode - 120 - mv v clk drx clock input voltage low-impedance mode - 120 - mv i 2 c-bus interface r on(sda) on resistance sda line 100 150 250 w r on(scl) on resistance scl line 100 150 250 w
2002 may 06 17 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 10 application information a typical application diagram of the tza1032 is shown in fig.4. as can be seen from this figure the clkp, clkn, datap and datan inputs allow differential data transfer for electromagnetic compatibility issues. input series resistors can be connected to obtain low voltage swing when using standard 3.3 or 5 v drivers. this will further reduce electromagnetic interference. this application diagram shows separated 3.3 v supplies to obtain maximum output performance. only few decoupling capacitors are needed for the total application. the forward sense loop is fully self-contained. only a forward sense diode has to be connected, which can be biased with an external voltage. the tza1032 can be mounted with flip-chip technology as a bare die on the flex foils. for this purpose the bond pads of the silicon die can be bumped with solder dots. in this configuration parasitic components (e.g. inductors) can be further reduced leading to even better performance of the tza1032.
2002 may 06 18 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth fsmin scl 3.3 w sda rdwr es es fs scl 3.3 v 3.3 / 5 v sda 26 25 24 23 22 21 20 19 18 17 16 15 14 40 41 42 43 44 45 46 47 48 49 laser (1, 2) 50 mgw504 51 52 39 38 v fs 37 36 35 34 33 32 31 30 29 28 27 1 choke flex-v3 main pcb choke c(bias) 100 nf c(laser) 220 nf 220 m f v bias 2 3 456 78 TZA1032UK (bare die) 910 11 12 13 fsplus lasp ameas cfs refl refh aez ivrefcon ivcon v ddd2 v dda2 v ssa2 v ssd v ssa v dda1 v ddd4 v ssd4 pad not bumped v ssa1 v ssd1 100 nf 560 nf 1.8 k w alpha- processing v ss v ssd3 test0 test1 test2 v ddd3 v dd3 v dd2 test_clk test_out0 test_out1 test_in0 test_in1 v ddd1 v ddd v dda3 v dd1 out1 out2 out3 v ddd v fs v dda v dd v ssd2 v ssd v ssa3 v ssa i2c_a0 opc clkn clkp datap datan irq i 2 c-bus 1.8 k w 1.8 k w 1.8 k w 10 k w encoder system controller pre- processor forward sense 220 m f 100 nf 100 nf 100 nf fig.4 typical application diagram for TZA1032UK on flex foil. (1) the loop format by out1, out2 and out3, laser anode, laser cathode, c(laser) and v ddd must be kept as small as possible. (2) the ground pad of c(bias) must be placed as close to v ss as possible.
2002 may 06 19 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 11 bonding pad locations note 1. all x and y coordinates represent the position of the centre of the pad in mm with respect to the centre of the die (see fig.5). symbol pad coordinates (1) xy v dd2 1 - 1.469 - 1.758 v dd3 2 - 1.2215 - 1.758 v ssd3 3 - 0.974 - 1.758 v ss 4 - 0.7265 - 1.758 test2 5 - 0.4775 - 1.758 test1 6 - 0.230 - 1.758 test0 7 + 0.019 - 1.758 v ddd3 8 +0.2665 - 1.758 test_in1 9 +0.5155 - 1.758 test_in0 10 +0.763 - 1.758 test_out1 11 +1.012 - 1.758 test_out0 12 +1.2595 - 1.758 test_clk 13 +1.5085 - 1.758 irq 14 +1.758 - 1.469 opc 15 +1.758 - 1.2215 i2c_a0 16 +1.758 - 0.974 v ddd1 17 +1.758 - 0.7265 v ssd1 18 +1.758 - 0.4775 v ssa1 19 +1.758 - 0.230 v ssd4 20 +1.758 + 0.019 v ddd4 21 +1.758 +0.2665 v dda1 22 +1.758 +0.5155 clkn 23 +1.758 +0.763 clkp 24 +1.758 +1.012 datap 25 +1.758 +1.2595 datan 26 +1.758 +1.5085 v dda2 27 +1.5085 +1.758 ivcon 28 +1.2595 +1.758 ivrefcon 29 +1.012 +1.758 v ssa2 30 +0.763 +1.758 refh 31 +0.5155 +1.758 refl 32 +0.2665 +1.758 cfs 33 +0.019 +1.758 ameas 34 - 0.230 +1.758 lasp 35 - 0.4775 +1.758 fsplus 36 - 0.7265 +1.758 aez 37 - 0.974 +1.758 v ddd2 38 - 1.2215 +1.758 fsmin 39 - 1.469 +1.758 scl 40 - 1.758 +1.5085 sda 41 - 1.758 +1.2595 rdwr 42 - 1.758 +1.012 es 43 - 1.758 +0.763 es 44 - 1.758 +0.5155 fs 45 - 1.758 +0.2665 v dda3 46 - 1.758 +0.019 v ssd2 47 - 1.758 - 0.230 v ssa3 48 - 1.758 - 0.4775 v dd1 49 - 1.758 - 0.7265 out1 50 - 1.758 - 0.974 out2 51 - 1.758 - 1.2215 out3 52 - 1.758 - 1.469 symbol pad coordinates (1) xy
2002 may 06 20 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 handbook, full pagewidth TZA1032UK mbl538 43 44 45 46 40 41 42 47 48 49 50 51 52 23 22 21 20 26 25 24 19 18 17 16 15 14 12345678910 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 scl sda rdwr es datap datan es fs clkp clkn i2c_a0 aez v dda1 v dda2 v dda3 v ddd4 n.c. v ddd3 test2 test0 test_in1 test_in0 test_out0 test_out1 test1 test_clk v ddd2 v ddd1 opc refl ivrefcon ivcon refh lasp v ss v ssa3 v ssd2 v ssa2 v ssa1 irq v ssd3 v ssd1 out1 out2 out3 v dd3 v dd2 v dd1 ameas fsmin fsplus cfs x y 0 0 fig.5 bonding pad locations.
2002 may 06 21 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 12 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. data sheet status (1) product status (2) definitions objective data development this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a. 13 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 14 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 may 06 22 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 bare die ? all die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of philips' delivery. if there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. there are no post packing tests performed on individual die or wafer. philips semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. accordingly, philips semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used. 15 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
2002 may 06 23 philips semiconductors preliminary speci?cation laser driver and controller circuit tza1032 notes
? koninklijke philips electronics n.v. 2002 sca74 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 753503/01/pp 24 date of release: 2002 may 06 document order number: 9397 750 08652

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